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RapidIO IP Core Features
The RapidIO IP core has the following features:
Chapter 1: About This MegaCore Function
Features
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Compliant with RapidIO Trade Association, RapidIO Interconnect Specification,
Revision 2.1, August 2009, available from the RapidIO Trade Association website
at www.rapidio.org
Successfully passed RIOLAB’s Device Interoperability Level-3 (DIL-3) testing
Supports 8-bit or 16-bit device IDs
Supports incoming and outgoing multi-cast events
Physical layer features
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1x/2x/4x serial with integrated transceivers in selected device families and
support for external transceivers in older device families
All four standard serial data rates supported: 1.25, 2.5, 3.125, and 5.0 gigabaud
(Gbaud)
Receive/transmit packet buffering, flow control, error detection, packet
assembly, and packet delineation
Automatic freeing of resources used by acknowledged packets
Automatic retransmission of retried packets
Scheduling of transmission, based on priority
Reset controller—fatal error does not require manual resetting
Optional automatic resetting of link partner after detection of fatal errors
Support for synchronizing with link partner ’s expected ackID after reset
Full control over integrated transceiver parameters
Configurable number of recovery attempts after link response time-out before
declaring fatal error
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Transport layer features
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Supports multiple Logical layer modules
A round-robin outgoing scheduler chooses packets to transmit from various
Logical layer modules
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Logical layer features
RapidIO MegaCore Function
User Guide
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Generation and management of transaction IDs
Automatic response generation and processing
Request to response time-out checking
Capability registers (CARs) and command and status registers (CSRs)
Direct register access, either remotely or locally
Maintenance master and slave Logical layer modules
May 2013 Altera Corporation
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